Introduction

This week I managed to add support for annotating interconnection delays of input/output vectors. What this means for you and your design you will see down below!

As the end of the project approaches, I am going to talk about the final steps to conclude this project.

SDF: Interconnection delays for input/output vectors

Two weeks ago, I announced that I had implemented interconnection delays in iverilog! If you have had a closer look (or read the summary), you know that there was still a big limitation: only scalar input/output ports could be annotated.

That means if you have a nice 32-bit RISC-V CPU and want to simulate it with some interconnection delays sprinkled on top, you would have to take something like this:

module nice_riscv_cpu (
  ...
  input [31:0] mem_rdata,
  ...
);

And convert it to something like this:

module nice_riscv_cpu (
  ...
  input mem_rdata0,
  input mem_rdata1,
  input mem_rdata2,
  ...
  input mem_rdata30,
  input mem_rdata31,
  ...
);

And combine the individual bits back into a single vector (or, if you want to call it that, a packed array).

This is now a thing of the past! No more passing a 32-bit input as 32-single-bit inputs - you can just use your designs as they are!

The PR for this feature can be found here: SDF: Interconnection delays for input/output vectors

A simple test with a 3-bit input and output vector was added to the test suite. However, the feature was also tested more thoroughly with my test suite and updated designs: interconnect-tests

This will hopefully make interconnection delays easier to use and also more useful.

The end of the project is nigh

You read that right - the end is nigh. The final deadline for my submission is the 25th of September and I plan to wrap everything up by 15th of September.

Until then, there is still some time left to work on features. I can think of two good options to work on: Either reannotation of annotated intermodpaths or starting to work on timing checks.

Since I believe timing checks add more value to this work, I am going to implement the $width timing check used in the SKY130 PDK.

Summary

With the deadline approaching, I have to keep in mind wrapping everything up properly. But so far it looks good.

I'll see you next week :)